Servo system and comparator



July 23, 1963 Filed Aug. 14, 1959 E. MUNDT SERVO SYSTEM AND COMPARATOR 4 Sheets-Shea?I l July 23, 1963 E. MUNDT 3,098,995

' sERvo SYSTEM AND CoMPARAToR Filed Aug. 14, 1959 4 sheets-sheet 2 July 23, 1963 E, MUNDT SERV()` SYSTEM AND COMPARATOR 4 Sheets-Sheet 3 Filed Aug. 14, 1959 k. .Bw

July 23, 1963 E. MUNDT SERVO SYSTEM AND COMPARATOR 4 Sheets-Sheet 4 Filed Aug. 14, 1959 NNN MNE, NNN NNQN ME @www er@ WMNNNNNNNN uw?. www @QR T 9 S n, wk IMQK United States Patent G 3,098,995 SERVO SYSTEM AND COMPARATOR Edward Mundt, Pasadena, Calif., assignor to Hycon Mfg. Company, Pasadena, Calif., a corporation of Delaware Filed Aug. 14, 1959, Ser. No. 833,880 15 Claims. (Cl. S40-146.2)

My invention relates generally to servo positioning and follower systems, and more particul-arly `to a new and useful positioning and/or follower system incorporating a novel comparator for comparing the contents of two digital counters or the like.

Generally, in a positioning system wherein a movable device is controlled in position within some frame of reference, command or reference position data is supplied and this data is compared `with data giving the true and instantaneous position olf the movable device within the reference frame. The difference between the compared data provides data, which can be positive or negative, describing the error in position between reference and true positions. The error data can be used to adjust the position of the movable device such that the error in position is reduced and finally removed. If the reference or command data varies, the `error data also varies so that correction of position by reduction of the error difference results in a continuously moving or follower system.

It is an object of my invention to provide a positioning and follower system wherein digital counters can be employed to store and supply data describing both .the reference and true positions of a movable device in a reference frame.

Another object of my invention is to provide a novel comparator for use in a positioning and/ or follower system employing digital counters, to compare the contents of the counters for an error control signal.

A further object of the invention is to provide an extremely accurate and eliicient servo positioning and follower system including digital counters for storage of reference and true positional data of a controlled device.

A still further object of this invention is `to provide a highly effective positioning and follower system for controlling the position and movement of a carriage along the length of a lead screw.

Briefly, and in general terms, the foregoing and other ancillary objects of my invention are preferably accomplished by providing a comparator `for comparing the contents of -a true position counter with that of a reference position counter to derive an error signal which is fed to a differential operational amplifier, the output of which is used to energize a servomotor that drives a lead screw to position a carriage riding thereon. Rotation of the lead screw and movement of the carriage is accompanied by actuation of means which generate suitable signals to alter the contents of the true posi-tion counter according to the instantaneous position of the carriage on the lead screw, until the contents of the true position counter are matched with that of the reference position counter. The contents of the reference position counter can be variable and the system is thus both a positioning and follower system. The comparator is also novel in structure and normally includes a digital and an analogue section to provide a digital and proportional control servo system. The digital section can be used alone as the com- 2 parator in a low gain servo system and still provide satisfactory control.

My invention includes other objects and features, some of which together with the foregoing, will be set forth in the following detailed description of 'a preferred` embodiment 'of my invention, and the invention will be more fully understood by reading the description with joint reference to the attached drawings, in which:

FIGURE 1 is a schematic block diagram of a preferred embodiment of my invention;

`FIGURE 2 is a -graph plotting control characteristics olf the preferred system `due to the digital section of a comparator in the system;

FIGURE 3 is another graph plottingy control kcharactelistics of the preferred system due to combined digital and analogue sections of the comparator;

FIGURE 4 is Ia block diagram of a preferred embodiment of a comparator which can be used in a digital servo positioning system;

FIGURE 5 is a schematic wiring diagram for explaining operation of the analogue section of the comparator in the preferred system;

FIGURE 6 is a wiring diagram showing connections of the outpu-t of the comparator with a differential operational amplifier;

FIGURE 7 is a detailed wiring diagram of the digital sect-ion of the comparator;

FIGURE 8 is a detailed wiring diagram of the analogue section of the comparator in the preferred system;

FIGURE 9 is a fragmentary wiring diagram illustrating a modification to the system for inverting output signals from the digital section of the comparator; andV FIGURES 10a and 10b, together, show circuitry for an extremely smooth running version of a digital servo positioning and follower system.

A positioning and follower system for controlling the instantaneous position of a carriage along a lead screw is shown in FIGURE 1. Comm-and data 10 which can be provided, for example, from punched or magnetic tape, controls the numerical contents of a reference position counter 12. The counter 12 is preferably a binary counter of conventional construction having fifteen binary stages, for example. The stages are connected in ordinary chain fashion and each stage comprises a Icommercial available bistable multivibrator binary circuit such as type PM7253, manufactured by the Walkrit `Company of Inglewood, California. Serial input pulses can be provided to the counter 12 on lead 14, and add-subtract control pulses can be supplied on lead 16 which trigger a bistable multivibrator 18, similar to a binary stage, that groverns whether the counter 12 will count forwards or backwards for each input pulse. The reversible counter 12 can be reset lby a pulse `appearing on lead 20.

An output from each stage is applied to a comparator 22 which includes a digital section 22a and an analogue section 22b. The outputs representing the first eight most significant digits, for example, are provided to the digital section 22a and the other outputs representing the remaining seven digits of the counter 12 can be supplied to the analogue section 2'2b of the comparator 22. A true position counter 24 which is identical to the reference position counter 12 provides outputs representing the fifteen digits of counter 24. 'Bhe outputs of counter 24 are applied to the comparator 22 in the same manner as the outputs of counter 12 are applied to the comparator 22. The outputs of counter 24 are compared with the `outputs of the counter 12 by comparator 22. A large (forward) conimand signal is obtained on output lead 26a than on lead Zeb if the contents of the reference position counter `12 is greater Ithan the contents of the true position counter 24, and a larger (reverse) command signal is obtained on output lead 261) than ion lead 26a if the contents of counter 12 is less than the contents of counter 24. Voltages (not necessarily yielding a resultant differential) can appear simultaneously on both leads 26a and 26b because of voltage outputs from the yanalogue section 22h but not from the output lof the digital section 22a, as will become apparent from the subsequent ensuing description of the comparator 22, and equal outputs on both leads 26a and 26h are obtained when the contents of counters 12 land 24 are equal (matched).

The signals on leads 26a and 26h are applied respectively to inverting and non-inverting inputs of a differential operational amplifier 28 to produce a positive (forward command) or negative (reverse command) output signal on lead 30. The output signal on lead 30 is chopped and `ampliiied by chopper and amplifier 3-2, and an alternating signal of proper phase is applied to servomotor 34 through lead 36. The servomotor 34 drives a lead screw 3S which, in turn, moves a carriage 40 along its length. The motor 34 is also suitably linked mechanically to actuate a sensitive single pole, double throw switch (not shown), which pole is spring loaded to a center, open position. The spring loaded pole of the switch can be rotatably mounted on Ian axle which is coupled to be driven by motor 34 through a slip clutch (not shown). When `the motor output shaft rotates in one direction, the pole of the switch is rotated a short distance in a corresponding direction until it is stopped by a switch Contact. This closes the switch and at the same time forces the slip clutch to slip as the motor 34 continues running. When the motor 34 stops, the pole of stlhe switch is returned to center position by spring force. The pole of the switch is similarly rotated in an opposite direction to close Ithe switch in a second position when the motor 34 rotates in a reverse direction. The pole of the switch is connected to a source of direct voltage and the switch contacts are both connected capacitively to the input of a pulse generator (not shown) which can be a conventional one shot multivibrator. The slip clutch, rotatable switch and pulse generator are indicated by block 42 iii FIGURE l. The pulse output of the pulse generator is applied through lead 44 to a bistable multivibrator 46 which controls forward or backward counting of the counter 24 for the input pulses fed thereto. The block 42 represents a means for triggering the bistable multivibrator 46 (changing its state) on reversal of direction of rotation of the motor 64. Other means for accomplishing this function can, of course, be utilized. A tachometer generator, for example, coupled directly to motor 34, can be used with a suitable anticipation circuit to sense reversal of motor direction, and control the bistable multivibrator 46. Extremely sensitive means of greater complexity can be employed according to the degree `of accuracy of operation that is desired, and the particular means described above is illustrative only of a simple and effective embodiment of such means.

' A small magnetic drum 48 is also mechanically connected tothe lead screw 3S and is rotated therewith. The drum 48 is magnetized in equal, closely spaced intervals around the periphery such that pulses are induced in magnetic pickup head 50 when the drum 48 is rotated. These pulses are fed to amplifier and Shaper 52, and are arnplilied and suitably shaped for Yapplication to the input of the counter 24 through lead S4. The pulses appear on lead 54 serially and cannot overlap because of the fixed spacing of .the magnetized elements on the drum 48. rThus, when the motor 34 rotates the lead screw 38 to drive carriage 40 and the magnetic drum 48, the contents of counter 24 is properly altered with the position of carriage 40 along the lead screw 38.l p y At index position, when the carriage 40 is at its leftmost position on the lead screw 38 in FIGURE l, a lamp 49a suitably mounted on the carriage 4l) directs a small beam of light towards `a photo transistor 56. The output Vsignal from the photo transistor 56 is used to trigger a monostable blocking oscillator 58 that produces a reset pulse output on lead 60. The true position ycounter 2.4 is reset by applying .the reset pulse to a corresponding emitter of each stage, in parallel to all of the counter stages 1n the usual manner. The contents of :the counter 24 'and the index position of the carriage 40 is thus synchronized properly. The maximum travel of the carriage 40 to the right in FIGURE l corresponds -to the maximum binary content of the counter 24, and other positions of the carriage 40 are, of course, proportionate to the contents of counter 24. Since the counters 12 and 24 each includes fifteen binary stages, the maximum content or capacity of each counter is 215, Kand this represents maximum travel to the right in FIGURE l on the lead screw 38. The digital section 22a of the comparator 22 in one version encompasses eight digital Istages which establish 4the position of carriage 4G on the lead screw 38 as determined :by the first eight most significant digits along the lead yscrew 38. 'Ihe analogue section 22b then establishes the carriage 40 inal position `according to the remaining seven digits of the 'compared `contents of counters 12 and 24. The carriage 40 indicates against a scale 62 having end graduation marks labeled 0 and 215 as shown lin FIGURE l. The intervening space is divided into equal `divisions of suitable separation. The Zero mark is, of course, the index or reference point and the llast mark indicates the farthest permissible travel to the right of carriage 4t) on the lead screw 38. This latter position corresponds to the maximum content of the two counters 12 and 24, as stated previously. i

System response as produced by the digital section 22a of the comparator 22 is indicated in FIGURE 21 A graph plotting the output speed of motor 34 as governed by the digital section 22a is illustrated by the positive and negative steps 64 and 66. If N is the commanded position for the carriage 40 and if the carriage 40 anywhere outside the exaggerated distance a-b shown in FIGURE 2, the motor 34 is energized either at full forward speed tor full reverse speed, depending on whether the carriage 40 is actually in the steps 64 or 66, respectively. I-f the comparator 22 lwas comprised entirely of digital binary stages; that is, a completely digital comparator, then the distance a-b can be eliminated and the steps 64 and 66 are extended to meet at N as indicated by the broken lines 64a and 66a. Such a completely digital comparator is fully effective to position the carriage 40 at the commanded position and is an extremely useful device in itself.

The lead screw 38 rotates at, `for example, 120 rpm.- when driven at full speed by the motor 34. Since the best servomechanism performance (highest gain) is obtained with a proportional control servo, the last seven digits of the counters 12 and 24 are compared in an analogue section 22h which provides proportional control within the interval a-b of the graphs shown in FIG- URES 2 and 3. Lines 68a and 68h in FIGURE 3 decrease linearly from a full forward .or full reverse condition proportionately `to zero at the commanded position N. The graph shown in FIGURE 3 illustrates system response for a commanded position N wherein the comparator includes both a digital section and an analogue section. It is noted that any output of the digital section 22a preferably overrides the output from the aiialogue section 22b until, ifor example, the first eight most; significant digits of counters 12 and 24 are matched, so. that a zero output due to the digital section 22a of comparator 22 is obtained. Thus, the carriage 40 must reach; either points a or b in FIGURE 3 and therefore within the seven least significant digits of the commanded position from either direction before proportional control becomes effective.

The comparator 22 including the `digital section 22a and analogue section 22b, and the differential operational amplifier 28 is shown in generally block diagram form in FIGURE 4. The digital section 22a comprises eight stages, for example, which `are labeled I-'1 through I-8. Stages I-2 through 'I-6 `are identical, and stages I-,1, I-7 and I-S are similar to the other stages except for the omission of some components which are not necessary in the latter stages. The analogue section 22b comprises two identical linear combiners, a reference position combiner including stages I-9a through I-15a which feed an operational amplifier 70a, and a true position combiner including stages I-9b through I-15b which feed an operational amplifier 70b. The corresponding stages such as stages I-9a and I-9b `are identical, and all of the stages l-9a through I-15a and I-9b through I-15b are similar. The outputs from the fifteen counter stages of the reference position counter 12 can be applied to the upper input terminals 72a and 74a of the digital sec-tion 22a and the analogue section 22b, respectively. Similarly, the outputs from the fifteen counter stages of the true position counter 24 can be applied to the lower input .terminals 72b and 74b of the comparator 22. The first eight most significant digits, -for example, of each counter 12 or 24 are applied to inputs of the digital section 22a, and the remaining seven digits of each counter are applied to inputs of the analogue section 22b.

As is well known, the base is 2 in a binary system, and only two numerals 0 and 1 are used to represent a number. The output signal from a `counter stage is obtained from the plate (or collector) of one of the two elements of a bistable multivibrator, in the counters 12 and 24. When the selected output anode voltage is low in a counter stage, the digit 0 is normally represented by that particular counter stage, and lwhen the selected output anode voltage is high, the digit 1 is normally represented. Of course, when one anode of a two-tube bistable multivibrator is high, the other anode will be low. Thus, since `a counter stage may represent the digit 1 for a specified state of the bistable multivibrator, and an output can -be obtained from either anode, the connected output anode voltage can be selected to be either high or low to indicate, respectively, the digit l or its (register) complement, the digit 0, when the counter stage (bistable multivibrator) is in Ithe specified state. A low voltage applied to the input terminals 72a, 72b and 74a, 74b can therefore represent either a 0 or l digit in the corresponding counter stage, depending upon which anode of the bistable multivibrator the output lead is connected to when the counter stage is in the specified state. For the counters 12 and 24, high and low output voltages of each stage are, for example -6 and 0 volts, respectively. Suitable output connections to those counter stages which feed the digital section 22a of comparator 22 are niade to anodes each of which provides a high output voltage (-6 volts) when the corresponding counter stage is in a state that represents the digit 1. The remaining counter stages which supply the analogue section 22b, however, have output connections to anodes that each provides a low output voltage (0 volts) when the corresponding counter ystage is in a state that represents the numeral 1. The complement of the digit existing in an analogue section counter stage is thus supplied to the analogue section 22b of comparator 22 in FIG- URE 4. Outputs from the digital section 22a appear on leads 76a and 76b and are respectively combined with the outputs of the analogue section 22b through blocking diodes 78a and 78b to provide inputs on leads 26a and 26b to the differential operational amplifier 28.

A linear combiner of the analogue `section 22b of cornparator 22 is schematically depicted in FIGURE 5. The stage I-9a comprises two resistors R16 and R17 which are connected in series, the combined resistance being labeled `R9a. The common junction between resistors R16 and R17 is connected to ground through a switch 89a, the other end of resistor R16 is connected to a voltage source ega, and the other end of resistor R17 is connected to the input of the operational amplitier '70a as shown. The operational amplifier 7tla has a feed- 'back resistor R18 and an effective input resistance R19 as indicated in FIGURE v5. The other stages I-10a, I-11a, I-12a, I-13a, I-14a, and I-1Sa are similar to the first stage I-9a. The output voltage e0 for the linear combiner is given by the following equation:

The value chosen for R10a is equal to 2R9a, that for Rlla is equal to 4R9a, and continuing for each stage in sequence with values of 211R9a where n is the total number of stages to the considered stage xless one. The values of resistances R9a 4and R18 are fixed, and all of the stage voltages 99a, eros, e11a 612a, 913s, @14s, and e15a are also Xed 'and equal in magnitude. If all of the switches S9a, S10a, S11a, S12a, S13a, S14a and S15a are closed, then e0 is zero. Opening switch 89a produces an output voltage e0 proportional t0 29a, and the further opening of switch S10a, in sequence, adds a proportional voltage ewa/2(=e9a/2) to the output voltage e0, or egg-l-ega/Z. This progresses additively in binary decreasing fashion with the continued sequential opening .of switches. lIt is noted that ythe value of resistor R17 is approximately 96K ohms while the input resistance R19 of the operational amplifier 70a is about 10 ohms. Since the resistors corresponding to R17 in the other stages I-10a, I-lvla, I-12a, I-13a, kI-14a, and I-15a are essentially doubled that for a preceding stage, olosuire of switch 89a, for example, to` gnound with other switches open does not alter the accuracy of the output Voltage e0 as defined lby the above equation. That is, because the input impedance of the operational amplifier 70a is relatively very low, current flow diverted from resistance 'R19 to resistor R17 by closure of switch S9a is negligible and imperceptible, and the Systern therefore produces an accurate output voltage e0.

The operational amplifier 70b, which is identical to 7 0a, is shown in somewhat fuller detail in FIGURE 6. A model K2-W Operational Amplifier rrranufacturedy by George H. Philbrick Researches, Inc., of Boston, Massaehusetts, its indicated as b. Circled numbers within the triangle 80h are pin numbers for the device, Iwhich is a plung-in unit. Pin 1 is connected directly .to an adjustable tap ot .a potentiometer R20 which is connected in a biasing circuit 82 as shown in FIGURE 6. The tap is normally adjusted to provide lapproximately 1.3 volts, for example, on pin 1 to pnoduce a zero output tor a zero input voltage. However, in the present invention the tap is adjusted in one version whereby a zero input produces -50 volts output, land -50 volts input produces a zeno volt output. Pin 2 is usually termed the inverting input and is oonnected yto all of the outputs of stages I-9b through I-15b. Pin 2 is also connected to pin 6, which is the output terminal, Ithrough series connected resistors R21 and R22. The series resistors R21 and IR22 comprise the soi-called feedback resistor. The resistor R22 can be adjustable as indicated. The other pins 3, 4, 5, 7 and 8 are connected as shown in FIGURE 6. The operational amplifier block 70a is identical to 70b including all connections `and component values.

The output of the operational amplifier 70a can be connected to gnound through three series connected resistors R23a, R24a, and R25a, and the output of the oper-V ational amplifier 7 0b can be similanly connected to ground through series resistors R23b, R24b, and RZSb. The anode electrode of diode 78a is connected to .the common junction betweenresistors P12311 and R2411. The series resistors R2311, and R2411, and R2511 comprise a voltage divider, and an input, pin 2, of the operation amplifier 80C is connected to both ythe anode electrode of diode 7811 and the common junction between the resistors R2311 and R2411 through ltwo series connected resistors RZ611 and R2711. Similarly, the series resistors R23b, `K241i, and R25b also comprise a voltage divider, and another input, pin l, of lthe yoperational amplier 80C is connected to both the anode electrode of diode 7 8b and the common junction between the resistors `R231b and R24b through two series connected resistors R26b and R27b. The two voltage dividers divide the output voltages from the operational ampliers 7011 Iand 70h by a factor of approxi-Y mately 10. The maximum output of -50 volts is thus reduced to approximately volts to the inputs of :the operational amplilier 80C; A fixed negative voltage or, for example -6 volts appears through one or the other of the diodes 7 811 and 78h whenever the inputs to digital section 2211 of the comparator 22 are not matched, and this greater voltage overrides any outpurt dilerential from the two analogue operational amplifiers 7011 and 70b which can have simultaneous outputs.

The operational amplifier 80C is connected as a differential operational amplier 28 having two inputs, a feedback resistor R23 connecting with one input and a grounding resistor R29 connecting with the other input as indicated in FlGURE 4. In FIGURE 6, a resistor R29 couneots the input from pin l to ground through the comparatively small resistances in the biasing circuit 84. The biasing circuit 84 is adjusted to produce la Zero output voltage for equal (zero diierential) input voltages to the differential operational amplifier 28. rIlhe input at pin 1 is a non-inverting input, and a negative input voltage on pin 1 pro duces -a negative output voltage on pin 6 and lead 30. This negative output voltage is the reverse command :signal for servomotor 34. The input at pin y2 is the inverting input, and a negative input voltage on pin 2 produces a positive output voltage on pin 6 and lead 30. This positive output voltage is the forward command signal for the servomotor 34. The input voltages to the differential operational amplifier 28 can be -6 volts from one or the other diode 7811 or 78b applied to one input and a smaller negative voltage applied to the other input from one of the operational ampliers 70a or 7011. When the overriding, full speed positioning of the carriage 40 is accomplished, so that the voltages through diodes 7811 and 7811 are both zero, proportional control commences and is dependent upon the gradual decrease of output voltage dii-terence between .the outputs of the analogue operational amplifiers 70a and 70h. The output voltage of the operational ampliiier 7017 equals that of 7011 when the carriage 40 is correctly positioned on the lead -screw 38. It should .be noted that [the diiereut corresponding stages of the two .linear combinors of the analogue section 22b are not necessarily matched in any particular sequence. That is, in FIGURE 4, the stage 1I-9b, I-lltlb, I-11b, 1 1211, 1-1311, I-14b, and I-15b can match the conditions of corresponding `stages 1 911, I-1011, I-11a, 1 1211, lli-1311, l-141z, and I1511 in a random manner.

FIGURE `7 illustrates in detail the circuitry of a preferred embodiment of the digital section 2211 of comparator 22. Stages 1 1 and l-2 are shown in detail, and together illustrate interconnections between successive stages. Stages l-Z through I-6 are identical, `and stages 1 1, 1-7 and 1 8 differ from them only in the deletion of unrequired elements. Stages I-7 and I-S are also detailed in FIGURE 7. The input terminal 7211 to stage 141 is connected to the anode of a diode 10011 and to the base of a transistor Qlb through a resistor R30b. The base of transistor Q1b is biased at +6 volts through resistor R3111. The collector of transistor Qlb is connected to -6 volts thro-ugh `a load resistor R32b, and the emitter is connected to ground. The collector of transistor Qlrb is connected to the lanode of diode 10211, the cathode of which is connected @to one end of a resistor R331), the other end being connected to -18 Volts. The other input -terminal 72b to stage 1 1 is similarly connected to the anode of a diode 10011` and to the baseof a transistor Q111. The transistor Qta corresponds to transistor Qib and is connected similarly with its collector connected to the anode of diode 10211, the cathode of which is connected to one end of resistor R3311, the other end being connected to -18 volts. The cathode of diode 10011 is also connected with the cathode of diode 10211 to resistor R3311, tand the cathode of diode b is connected with the `cathode of diode 10211 to the resistor R33b.

The cathodes of diodes 10011 and 10211 are connected through resistor R3411 to the base of transistor Q2, and the cathodes or diodes 10011 and 10211 are similarly connected to the base of Q2 through resistor R341). The collector `of transistor Q2 is connected to the base of another transistor Q3 through a resistor R35. The transistors Q2 and Q3 are connected in grounded emitter circuits like transistors Qla and Qlb. The collectors or transistors Q2 and Q3 tare connected respectively to the interconnecting leads 10411 and 10411. The output dead 7611 is connected to the cathodes of diodes 10011 and 10211 through a blocking diode 10611 which is oriented to pass negative output signals, and the output lead 76b is similarly connected to the cathodes or diodes 10017 and 10211 through `diode 10611. Stage `I--2 is similar to stage I-1 with the addition of diodes 10811 and `llltlb, the anodes of which are both connected to lead 10411 and their cathodes being connected to the cathodes of diodes 11011, 11211 `and b, 11211, respectively. The lead 104b is connected to the base of a transistor Q4 which corresponds to transistor Q2 in stage I-l, and the collector of transistor Q4 is resistively connected tothe base of transistor Q5 which corresponds with the transistor Q3. The outputs from stage I-2 to output leads 7611 and 76b `are through diodes 11411 and 11417 which correspond with diodes 10611 and 10611, respectively. Finally, it can be seen that in stage 1 7, a transistor corresponding to transistor Q3 in stage 1 1 has been omitted, and the components corresponding to resistors R3411 and R34b together with the following transistors Q2 and Q3 have been omitted from stage 1 8.

Operation of the digital section 2211 can be explained by rst considering different inputs to stage I-l. inputs to stage I-1, tfor example, represent the most sigincant digits respectively of the counters 12 and 24. If a l digit appears on input terminal 72a of stage I-l, this` means that -6 volts is applied thereto. If a 1 digi-t exists on input terminal '72b of stage l-1, the carriage 40 is already correctly positioned within the control range of the most 'significant command digit, but if a 0 digit exists on the input terminal, the servomotor 34 must be properly energized to bring fthe carriage 40 into the domain ofthe most signicant digit. When -6 Volts exists on the input terminal 7211ot stage 1 1, the -6 volts is applied to the base of transistor Q1b, turning on the transistor Q1b so that the anode of diode 10217 is placed at substantially 0 volts. Alll of the transistors in the digital section 2211 of comparator 22 are operated saturated on and function `aS switches. The -6 Volts is lalso applied to the anode of diode 10011. lit the input terminal 72b of stage I-l is also at -6 volts (a 1 digit), then the -6 volts is applied to transistor Q111, turning on the transistor and placing the anode of diode 10211 at substantially 0 volts. The -6 volts is also applied to the anode of diode 1Mb. Resistor lR3311 and the diodes 10011 and 10211 comprise an and circuit, and resistor R33b and `diodes 10019 and 10211 is similarly :an and circuit. Since one of the diodes of each and circuit has an anode at zero potenti-al, those diodes, 10211 and 10211, will conduct increased current to the 18 volts source. The result lis that 0 volts appears on the cathodes of diodes 10011, 10211 and 10019, 10217, and are yapplied respectively to both cathodes or `diodes 10611 and 106b. The voltage on the connected output l of the corresponding or circuits in other stages.

leads '76a and 76b from diodes 106a and 106b, respectively, is therefore vol-ts.

If -16 volts exists as before on input terminal 72a and 0 volts appears on terminal 72b of stage I-l, the anodes of diodes 100:1 Sand 102b remain unchanged iat -6 volts and 0 volts, respectively, but 0 volts novv is applied tothe anode of diode 100b and to the -base of transistor Qla turning off the transistor so that -6 volts appears on the anode ot diode 1025:. The cathode of diode 10612 is thus at 0 volts, and since -6 volts is applied to both diodes 100a and 102g, the cathode of diode 106a is placed at -6 volts which is transmitted to lead 76a. This negative output voltage is applied to the differential operational amplier 28 through diode 78a (FIGURE 4) as described previously and produces a positive forward command signal to servornotor 34. The negative output voltage is biocked out of the other digital stages by output diodes such as diode 1.14a of stage I2 similar to the diode 106a. The zero volts on the other output lead 76b is ineffective.

If zero volts exist on both input terminals 72a and 72b of stage L1, the anodes of diodes -100a and 100b will be at 0 volts and the anodes of diodes 102a and 102b will he at -6 volts. The transistors Qla and Qlb thus convert a low input voltage into a high output voltage or a high input voltage into a low output voltage, and are thus herein designated converters. The 0 volts on ldio-des 100a and 100b permits increased current conduct-ion tothe -18 volts source, and the cathcdes of output diodes 106:1 and 106b rare both placed at 0 volts. Thus, 0 volts are provided to the output leads 76a and 76b lby diodes `106e and 106b, respectively, 'for 0 digit inputs to the stage I-1. If -6 Volts I(a l input) existed on input terminal 72b, With input terminal 72a retaining the zero volts (a 0 input), the diodes 100a and 102a are both placed at zero volts, and the diodes 100b and 102b are place-d at -6 volts. Accordingly, the cathode of diode 106a is at 0 volts and the cathode of diode 10611 is at -6 volts. The result is that the output leads 76a, due to stage 1 1, is placed at 0 volts and the output lead 76b is placed at -6 volts. The negative voltage on output lead 76b produces a negative output voltage from .the differential operational amplifier 28 which drives the servorrnotlor 34 in a reversed direction.

When both of the cathodes of the diodes 6a and 10619 are at 0l volts, the base of transistor Q2 is slightly positive by voltage divider action of its base bias resistor (to +6 volts) in series with resistors R34a and RS4/b (which are in parallel), The transistor Q2 remains cut off such that a negative voltage is applied to the base of transistor Q3 so that the transistor Q3 conducts and its collector is at essentially 0 volts. The transistors Q2 and Q3 are controlled converters that provide proper high or low control signals to the next stage I-2. Lead 104a connected to the collector of transistor Q2 is thus at essentially -6 volts which is applied to the anodes of diodes 108a and 108b in stage I-Z. The -lead 104b connected to the collector of transistor Q3 is at 0 volts and connected to resistor R35 fin stage I-Zt The 0 volts on lead 1041 has no effect on the `off condition of transistor Q4 when the cathodes of diodes 114i: and 1Mb are at 0 volts; that is, when the two inputs to stage I-2 are the same or matched. The resistors R34a and R34b essentially comprise an or circuit (less the usual diodes) together with the bias resistor connected to the base of transistor Q2. The resistor R36 (stage I-2) is also part If either of the cathodes of diodes 10611 or y10611 is at -6 volts; that is, vvhen the inputs to stage I-l do not match, the -6 volts through either resistor R34a yor R34b produces a suitable negative voltage on the base of the transistor Q2 which turns on the transistor. The collector of transistor Q2 drops to essentially 0 volts and a positive voltage is .applied to the base of transistor Q3 which cuts oil lthat transistor. Thus, lead 104a provides :a zero voltage to the anodes of diodes 10801 and 108b while lead 104b provides -6 volts to the resistor R36. The zero voltage on diodes 10851 and '10811 clamps the cathodes of output diodes 114e and 1Mb respectively to ra zero output voltage irrespective of Whether any pair of the diodes e, 1'12a and r1.10b, `112b are at A-6 volts. An interlock is thus provided which prevents any Output from stage lI--Z until inputs to stage I-l are matched.

The `--6 volts yon resistor R36 pr-oduces a negative voltage on the base of transistor Q4 which turns on the transistor Q4 so that -a zero clamping voltage also appears on lead 116er corresponding to lead 104a, and is applied to the following stage. The essentially 0r volts on the collector of transistor Q4 cuts o? transistor QS. The 6 Volts then on the collector of transistor Q5 is applied through lead 1.16b to turn on a transistor in the next stage which corresponds to transistor Q2 or Q4 to produce a zero clamp voltage for the second next succeeding stage. This is continued throughout the rest of the digital stages to prevent any output from appearing from any particular strage until the next preceding stage has matched inputs. Stage I-7 does not require a transistor correspondring to the transistor Q3 or Q5 since stage I-S is the last digital stage and which does not need an interlock.

The analogue section 22b has been shown and described generally in FIGURE 4, and its operation explained previously with reference to FIGURE 5. FIGURE 8 shows in detail the structure of the stages I-9a, -I-9b, I-10rz, I-lGb, etc. The transistors Qa, Q9b, Q10zz, Q10b, etc. are operated as switches and are either on (saturated) or oli. When zero volts (a 1 digit for the analogue stages of counter 12) are applied to input terminal 74a of stage I-9a, for example, the positively biased base of transistor Q9a` remains somewhat positive and the transistor is cut olf. rIhis corresponds to an open switch 89a in FIGURE 5. The voltage egg (FIGURE` 5) corresponds to the -50 volts supply voltage, and the resistors R116 and R17 are llabeled identically in FIGURE 8. When transistor Q9a is cut off, that porti-on of the output voltage e0 on lead 11361 due to stage I-9a, given above in the output equation as (R18/R9a)e9a, appears on the output lead 118s. When -6 volts (a 0 digit for the analogue stages of counter 12) is applied to terminal 74a, the transistor Q92: is turned on because -of a negative voltage now appearing on the base of the transistor. This, of course, places the common junction between resistors R16 and R17 at essentially 0 volts, and drops the output voltage on lead 118e from stage I-9a to zero. As can be seen in FIGURE 8, there is no interlock device, and the stages I-9a through I-lia'a las employed in FIG- URE 4 can be switched on or olf without any definite sequence. Since stages I-9b through I-15b are identical to stages I-9a through I-lSa, the former stages operate in the same manner as described above for the latter.

if all of the inputs such as 74b have a zero voltage input (all l ldigits in the corresponding last seven stages of counter 24), a negative voltage .of '50 volts would be provided to pin 2 of the operational amplier '70b (FIG- URE 6). Since pin 2 is the inverting input, a positive output voltage of +501 volts lwould appear at the output. A negative output voltage, however, is desired, to correspond with the negative .output voltages from the digital section 22a of the comparator I22'.. In order to achieve this, the zero adjustment bias circuit `82 is adjusted as mentioned previously to shift the zero point such that the -i-SOr volts is reduced to 0r Volts. This zero adjustment would then change a 0i volts output from the operational amplier 70b to y--50` Volts, which is produced when all of the inputs 74b have -6 volts applied thereto (all 0 digits in the corresponding last seven stages of counter 24). This -50 volts is divided down to approximately -5 volts as described previously, and can be overridden by the -6 volts from the digital section 22a, when present. The zero adjustment `bias circuit for the operational arnplier 70u can he similarly adjusted to provide negative output voltages.

'It is to be noted that since 0 volts at the input of operational ampliiier 7tlb corresponds with -50 volts output, and -50 volts at the input of 79b corresponds with O volts lat its output because `of the .above bias adjustment zero shift, as the input voltage to 7Gb increases negatively, the output decreases negatively. In short, an increasing input produces a decreasing output and a decreasing input produces an increasing output. For this reason, the complements of the digits in each of the analogue stages of counter 24 have been provided as inputs to the analogue section 22b. Thus, for the analogue stages or the last seven stages of counters l2 and 24, the complements of the number content for each of these stages are provided to the yanalogue section 22b of comparator 22. Since the complement of a number increases for a decreasing number and decreases for an increasing number, the above condition wherein an increasing input produces a decreasing output and a decreasing input produces an increasing output is satisfied.

There is an advantage, however, in having normal positive output voltages from ithe operational amplifiers 70a and 7ilb `for negative input voltages thereto. The advantage is that of a wider linear operational range for the operational ampliiiers without saturation. There is a tendency for an earlier saturation limit of the common commercial operational amplifiers when bias adjustment is unusually high, as may be the case where the bias is adjusted to shift the normal zero level excessively. In the above instance where bias is adjusted so that volts input normally producing 0 volts output is changed -to --50 volts output, the limits for reliable operation without tendency of saturation is reduced. An alternate arrangement Which would permit use of the normal positive output voltages from the operational yampliiiers '70a and 7Gb can be obtained by simply inverting the -6 volts that can appear on leads '76a or 76b to +6 volts, and then reversing the orientation of diodes '78a and 7812. The use of complement inputs to the analogue section 2211 is not changed in such an arrangement since as the input voltage to operational amplifier 70a or 70h increases negatively (from 0 volts), the output decreases negatively (increases positively from 0 volts), :and as the input voltage -decreases negatively (from --50` volts) the output increases negatively (decreases positively from +50 volts), as before.

FIGURE 9 illustrates the modiiication necessary to invert the -6 volts that can appear on leads 76a or 76b to +6 volts. Transistors Q6a and Q6b are inserted in leads '76a and 761'), respectively, before diodes 78a and 78b which correspond to diodes 78a and 78h. The transistors Q6a and Qb are NPN type transistors as contrasted to the rest which are PNP type transistors. The collector of transistor Q66: is connected to +6 volts through a load resistor R370: and its emitter is grounded. The base of the transistor Qa is connected to the +6 volts supply thro-ugh resistor R38a, and the :base is also connected to lead 76a through resistor R39a. The collector of transistor Q6a is connected to the Ianode of the diode 73a. When O volts exist on lead 76a, the base of transistor Q6@ is positive and the transistor is turned on (conducts) to provide substantially 0 volts to the anode of diode '78a'. A negative voltage of -6 volts on lead 76a, however, cuts off the ytransistor Q6a such that +6 volts is applied to the anode of diode '78a' and which is transmitted by the diode. Thus, a -6 volts input is inverted into +6 volts, and 0 volts input is correctly inverted to remain 0 volts. The transistor Q6b is connected exactly as Q6a and functions in like manner as an inverter. Since a positive (+6 volts) output is provided through diode 78h', for example, fthe operational amplifier 7Gb (FIGURE 6) can have its bias circuit 82 adjusted normally to provide approximately 1.3 volts on pin l, which produces 0` volts output on pin 6 for 0 volts input on pin 2 and an increasing (negative) input produces an increasing (positive) output. The operational ampliiier 70a can be adjusted similarly since a positive output is provided through diode 78a'. Positive input voltages are now applied to the differential operational amplifier 28 (FIGURE l) with the result that negative output voltages therefrom become forward command signals and positive output voltages are reverse command signals. These output voltages are chopped and amplified as before but are applied to mot-or 34 on reversed (phase windings) leads. It is, of course, equally lfeasible instead to interchange lead connections at the two inputs of the differential operational amplifier 28 (leads to pins l and 2 o-f the operational amplifier Stic in FIGURE 6 can be cross switched).

The digital section 22a as illustrated in FIGURE 7 can be described clearly in logical terms. Considering stage 1 1, for example, the diodes 1G0a and 102:1 are connected in a first and circuit having two separate inputs and an output. The transistor Qla is connected as a converter which converts 0 volts on input terminal 72b to -6 volts output, or -6 volts on terminal 72b to 0 volts output. It is noted that in logical terms, the converters ldesignated herein `are commonly termed inverters because the device inverts a 0 digit into a l digit, and vice versa. The output of converter Qla is connected to an input (anode of diode 102a) of the above and circuit, and the other input (anode of diode 104m) is connected to input terminal 72a. A second and circuit including diodes lltltlb and 102i) corresponds to the above described tirst and circuit and the transistor Qlb is connected as a converter corresponding to the converter Qla. Input terminal 72a is connected to converter Qib which has its output connected to an input of the second described an circuit, the other input of this and circuit being connected to input terminal 72b.

The output from each of the two and circuits are connected to respective inputs of an or circuit including resistors R34a and R34b having an output connected to the base of transistor Q2. The output of the first and circuit is also connected tot an input (diode 1fi6a) of a multiple input or circuit including diodes 106:1, 114a, etc. Similarly, the output of the second and circuit is also connected to an input (diode l06b) of a multiple input or circuit including diodes 106]), 114b, etc. Transistor QZ is connected as a converter (or inverter in co-mmon logic terminology) and the transistor Q3 is similarly a converter. The output of converter Q2 is` connected to diodes 108e and 108b which respectively comprise third inputs to and circuits in `stage I-Z which correspond with the first and second and circuits previously described for stage I-l. The output of converter Q2 is `also connected to the input of the converter Q3, the output of converter Q3 being connected to resistor R36 (of stage 1 2) which is the third input to an or circuit corresponding to the one in stage I-l.

The foregoing summary of the logic of the digital section 22a can be extended Vaccordingly to provide a full and complete description of my invention. Each of the logical elements is not limited, of course, to any specific means. For example, the converters can be any suitable device as may be desired or required, and can include ordinary switches, electron tube circuits, pulse transformers, etc. Similarly, the or and and circuits are not limited to diode circuits but can also include magnetic core devices, ordinary switches, etc. which are suitably connected in the desired or or and circuitry. Further, the logic of the invention, or any portion or part thereof, is also applicable and useful in synchronous systems, as in computer circuits which are synchronized by a clock source.

While the system described above is reversible in operation, the carriage `40 (FIGURE l) is actually positioned accurately without overshoot in any control movement. That is, if the carriage 40 is to be positioned from some point, for example, in the forward direction to a point N, the carriage 40 is driven by servomotor 34 generally according to curve 64 and 68a (FIGURE 3) to point N and does not involve any part of curve 68b to return the carriage 40 `because of any overshoot. It should be noted that FIGURES 1, 2 and 3 are generally applicable to the overall invention, but are particularly descriptive of the version of invention illustrated in FIGURES 10a and lil-b. For example, when an overriding Voltage appears on lead 76a or 7Gb (FIGURE 4) through the diodes 78a or 78h, respectively, the differential output voltage from the differential operational amplifier 28 will be actually dependent upon the output voltages of the operational amplifiers 70a and 7Gb. Since the output voltages of the operational amplifiers 70a and 7Gb are respectively dependent on the digital contents of the last seven digit stages of counters 12 and 24; the output voltage of each increases negatively with the number in the last seven counter stages according to the equation given above in connection with FIGURE 5, the overriding output voltage combined with the opposing output voltage from operational amplifiers 70a or 70b produces a differential output voltage from the differential operational amplifier 28 which is largest for zero volts output from 70a or 70'b and smallest for `-5 volts (divided down from -50 volts) output from 70a or 7Gb, as combined with the particular overriding voltage of 6r volts. Thus, the smaller the number in the last seven counter stages (in order of significant digits), the greater will be the differential output voltage produced from the differential operational amplifier 28. The servomotor 34 is therefore driven at full forward or reverse speeds because of overriding voltages only when, for example, the most significant digit of each of the last seven stages of counters 12 and 24 are zero. That is, the speed of servomotor 34 is governed principally Iby the 'binary number contents in the last seven digit stages of the counters 12 and 24, in the above described system.

The system described above (FIGURES l and 4) operates very well in a servo positioning system, and in a `slowly changing servo yfollower system, wherein the conten-ts of the reference position counter 12 is not changed rapidly (essentially fixed relative to the changing contents of the true position counter during each matching o-r positioning interval). The digital section 22a alone can, of course, comprise a comparator' for use in a servo system which does not require proportional control, as in a relay type or discrete incremental control system. There are many systems that are particularly suited for discrete, incremental control. In this instance, the analogue section 22h is simply deleted and the outputs of the digital section 22a are applied directly to the differential operational lamplifier 28. 'Iihe digital stages of the digital section 22a can be increased as necessary to accept all of the outputs from the counters 12 and 24. Complement-s would not then be required with the omission of the analogue section 22b.

FIGURES i10a and 10b, together, illustrate a modified version of comparator 22 and its connection with the differential operational 'amplifier 28 to produce a desirable output signal therefrom, vvhereby a continuous positioning and follower servo system is obtained. The circuit of FIGURE 10a is somewhat similar to that shown in FIG- URE 4. In the circuit shown in FIGURE 10a, there are fifteen digital stages I-1 through I-'6r, I-7, I-S, and I-9 through I- which accept the digital outputs of the reference position counter 12 and the true position counter 24 (FIGURE l). The :analogue section 2211 is now actually a Weighting section connected to receive the individual outputs from the additional digital stages I-9 through I-15 as indicated in FIGURE 10a. The output of upper and lower halves of the analogue section is in progressively diminishing steps of differential output voltage which is linearly averaged by the servornotor. As in the original digital section 22a, the Iirst and last two digital stages (I-1, I-14 and I-15) are slightly different from the rest of the digital stages in that portions of the interlock circuitry are not required. The first eight most signiiicant digit outputs from the counters 12 and 24 are applied respectively to terminals 72a and 72b as before. However, the remaining seven (complement) digit outputs from the counters y12 and 24 are no longer applied to the input terminals 74a and 7r4b of the analogue section 22h, but are applied instead to terminals '74C and 74d of the enlarged digital section of the comparator 22, and the outputs of the additional stages I-9 through I-15 are applied respectively to the corresponding stages of the analogue section 22h. Interlocks yare provided 4between Iall of the fifteen digital stages, so that sequential matching of digital stages is performed and misleading algebraic difference or phase conditions of the analogue section digits that may arise in the servo comparator version shown in FIGURE 4, and presented to the servomotor, are avoided during rapid follower operation.

The combined outputs of digital stages 1 1 through 1 6, I-7 and I-S' appear on leads 76a and 76b similarly as before. The outputs on leads 76a and 76b are inverted and combined with the outputs of the analogue section which are coupled through resistors R23a and R23b to .the inputs of the operational amplifier Stic, which is connected -as Ia differential -operational ampliier. Since there vare interlocks between :all of the digital stages, driving signals do not appear simultaneously from leads '76a or 76b and from operational amplifiers 70a or 70h (which have balanced, equal outputs that do not produce a driving differential output signal when lead 76a or 76b is active). The output signals on leads 76a and 76b are also used to increase the positive or negative output voltage from operational amplifier C to a saturating output voltage (in this version) when the signal on leads 76a or 76b persist longer than, for example, ll milliseconds. The saturating output voltage saturates the servo amplifier (32) which then drives the servornotor (34) at full forward or reverse speeds until such time that the inputs to` digital stages I-1 throuogh 1 6, I-7 and I-8 are matched, and Zero outputs exist on leads 76a and 76b. The circuitry for accomplishing the inverting and saturating actions just described is shown in FIGURE 10b. The leads 76a and 76b are continued from FIGURE 10a, and resistors R23a and R23!) are shown again (duplicated) in FIGURE 10b to indicate accurately the connections of these resistors in the circuit of FIGURE 10b. Transistors Qc and Qd correspond with transistors Q6a and Q61), respectively, of FIGURE 9, and are inverters. The inverted output from transistors Q6c and Qd are coupled to the analogue output :as before through diodes 7Sc andI 78d, corresponding with diodes 78a and 7817 of FIGURE 9. The diodes 78e and 7 8d are respectively back biased negatively when transistors Q6c and Q6d are conductive. The input network .and associated circuitry to the operational lamplier 80C is generally similar to that shown in FIGURE 6. An adjustable potentiometer R40 connecting -6 volts to ground provid-es a negative center balance point voltage to reduce the positive voltage which is applied to the inputs of the openational rampliiier 80C from either the digital stages through diodes 7 8c or 78d, or the analogue stages through operational ampli'ers 70a or 7Gb, so that operation yof the operational amplifier 80C is kept within its linear operating range iat all ti-mes, and particularly to prevent an excessively large positive voltage `from being applied `to lboth inputs of the operation-al arnplifier 80C during quiescent conditions. For example, when the digits of corresponding counter stages of counters 12 and 24 are matched, 0 volt out-puts lare applied respectively to corresponding inputs of the analogue comparator stages such that -50 volts are provided lto both operational amplifiers 70a and 7 0b, to produce +50 volts outputs from each. These outputs are both divided down to volts, and then applied to separate inputs of the differential amplifier 80C. This maximum input voltage (5 or 6 volts) preferably should not be applied simultaneously to both inputs of most ordinary, commercially available difierential operational amplifiers, especially for extended periods of time. rIhe bias for each of the operational amplifiers 70a and '70b is adjusted to produce a correspondingly suitable zero output voltage from each operational amplifier, for a Zero input thereto. A positive or negative linear differential output signal is o'btained from the operational amplifier Stic through isolating resistor R41. Inputs to the operational lamplifier 80e are suitably connected to produce a positive forward command signal and a negative -reverse command signal for the servomotor.

The lead 76a is also connected to the base of transistor Q7a which is connected as an inverter having an output clamped negatively to ground by diode 12Go. A series resistance-capacitance circuit including resistor R42a and capacitor Cla is connected in parallel with .diode 12Go. Resistor Ril-3a connects the clamped and generally linte- -grated output to control a negative diode limiter comprising diode 12241 connected in series -with resistor R44a. The cathode of diode 122a is connected to the output lead 30 of the operational amplifier 80C, the resistor R43a is connected to the common junction between diode 122:1 and resistor R44a, and the other end of resistor R44a is connected to a negative supply voltage of +18 volts. When 0 volts appears on lead 76a, the transistor Q7a becomes conductive such that its collector is at essentially 0 volts. Capacitor Cla discharges quickly through resistor RlZa and Ithe tr-ansistor Q7a, and the anode of diode 122:1 is maintained at a negative back biasing potential sufiicien-t to buck any negative output voltage from operational ampliiier 80C or a negative saturating output voltage provided to output lead 30 through resistor R43!) and diode l22b from a negative supply of -18 volts. When -6 volts exists on lead 76a, the transistor Q7a is cut ofif and the capacitor Cla is gradually charged positively. The collector of transistor Q7a is resistively connected to approximately +18 volts and the anode of diode 122a is placed at approximately +6 volts after ll milliseconds, so that a postive saturating output voltage is provided to 'output lead 3f) through diode 122:1. The cathode of diode i221; is positively back `biased sufficiently Ito prevent forward conduction through it (transistor Q7b is conducting). Thus, when the first eight most significant digit stages of the digital section (FIGURE 10a) do not all produce a 0 volt output on lead 76a after, for example, l1 milliseconds, the output of the diferential operational amplifier 28 is increased Iby an auxiliary positive saturating voltage which is provided through diode 122a.

Transistor Q7b restores the original polarity of the output signals from transistor Qtid to that appearing on lead 7617. The output of transistor Q7b is clamped positively to ground 'by diode 120b and the Ibalance of the circuit is similar to that for the transistor Q7a. A positive diode limiter comprising diode 122b connected in series with resistor R44!) (connected to a positive supply voltage) is :connected in a circuit which provides a negative saturating output voltage -on lead 30 when -6 volts exis-ts on lead 7 6b more than ll milliseconds, for example. When t0 volts exists on ylead '7611, a negative voltage is applied -lto the base of transistor Q7b such that the PNP type tran- ;sistor is conductive and the collector is at essentially 0 volts. The capacitor Clb discharges quickly through resistor R42b and the transistor Q7b, and the cathode of ldiode 122i) is then maintained at a positive `back biasing potential suflicient to buck any positive linear output voltage from the operational amplifier 80C or a positive saturating outpu-t voltage provided to output lead 30 through resistor R43a and diode 122a from a positive supply of +18 volts. When -6 volts appears on lead 7 6b, approximately O volts `is applied to the base of transistor Q'7b and the transistor ,is cut off. The result is that capacitor Clb gradually charges negatively and the cathode of diode l22b is gradually reduced to and held at approximately -6 volts after, for example, 1l milliseconds and a negative saturating output voltage is thus provided to output lead 30 through diode 122b. The anode lof diode 122a is negatively back biased sufficiently to prevent conduction through it by the negative saturatin-g voltage on lead 39 (transistor Q7a is conducting). Thus, when all of the first eight most significant digit stages of the digital section (FIGURE 10a) do not all provide a 0 volt output on lead 7Gb, the output of the diiierential amplifier 2S `is increased by an auxiliary negative saturating voltage which is provided through diode 12211.

A negative voltage on lead 76a should produce a positive forward command signal to #servomotor 34, and a negative voltage on lead 76b should produce a negative output voltage from the differential amplifier 28 to drive the servomotor 34 in a reversed direction. Since -6 volts would appear only on leads 76a or 76h when the digit contents of the first eight most significant digit stages of counters 12 and 24 (FIGURE l) are not matched and interlocks are provide-d lbetween all of the digital stages, the output from the diterential amplifier 28 is restricted to a positive linear range output command signal when -6 volts appears on lead 76a, and is restricted to a negative linear range output command signal when -6 volts appears on the lead 76h. Accordingly, the output of the differential amplifier 2S is increased by a saturating voltage of a correct polarity, and the saturating voltage is made available only after a suitable time delay determined by capacitors Cla and Clb and the load .resistors of transistors Q7a and Q7 b, respectively. These delayed saturating voltages do not produce noticeably abrupt or sharp responses of the servomotor 3d as may result from unwarranted strong saturating signals which are unnecessary or undesirable except for large, prolonged digital differences in counters l2 and 24. In paiticular, the charging of the capacitor Cla, for example, during changes of signal voltage lon lead '76a from 0 Ito -6 volts causes a gradual transition from the permissible negative back biasing voltage on diode 122a to a saturating positive driving voltage output through the diode 22a. The charging of capaci-tor Clb acts similarly on the permissible positive back biasing voltage on diode 122b to produce a saturating negative driving voltage output through the diode 122b follow-ing changes of signal voltage on lead 76h from 0 to -6 volts. The capacitors Cla and C111 are, however, discharged rapidly for changes of signal voltage on leads 76a and 76h from -6 volts to 0 volts. A limiting diode back biasing voltage condition is thus changed to a saturated output driving voltage much less rapidly than change of the saturated output driving vol-tage to the limiting diode back ybiasing voltage condition. The delay time of ll milliseconds is selected to be approximately equivalent to sixteen changes of the least significant digit in a counter. The maximum -rate that the least significant digit is changed is once every 680 microseconds, for example. A'brupt starts `and stops are eliminated, and a smooth transition of `forward and reverse motion of the servomotor 34 is produced. The version of servo system resulting from the circuitry shown in FIG- URES 10a and 10b Ihas yielded an extremely smooth running and effectively operating positioning and follower system.

It is to be understood that the particular embodiment of my invention described above and shown in the drawings is merely illustrative of and not restrictive of the broad invention, and that various changes in design, structure and arrangement may be made without departing from the spirit and scope of the broader of the appended claims.

I claim:

l. In a servo system, a first (m+n)stage digital counter; a second (m+n)stage digital counter; a comparator having a digital section and an analogue section,

the digital section including means for comparing the contents of the m stages of said first and second counters and lgenerating a first output signal of predetermined magnitude when the contents of the m stages of said first digital counter is greater than the contents of the m stages of said second digital counter, and generating la second output signal of the same predetermined magnitude when the contents of the m stages of said second digital counter is greater than the contents of the m stages of said first digital counter, and the analogue comparator section including means for converting the contents of the n stages of said first digital counter into a third output signal of magnitude proportional Ito the contents of the n stages thereof, means for converting the contents of the n stages of said second -digital counter into a fourth output signal of magnitude proportional to the contents of the n stages thereof, the third and fourth output signals having a predetermined maximum magnitude srnaller than the predetermined magnitudes of the first and second output signals, and means for combining the first 'and second output signals respectively with the third and fourth output signals; and a differential operational amplifier having the combined output signals applied thereto to provide an output signal of one polarity when the contents of said first digi- -tal counter is greater than that of said second digital counter and of reversed polarity when such condition is reversed, the output signal of said differential operational Aamplifier being proportional to the difference in magnitude of the combined signal pairs.

2. The invention according to claim l including, in addition, a device movable within a reference fram-e, a servomotor vadapted to drive and position said movable device in the reference frame, said servomotor being responsive to the output of said differential operational amplifier, and wherein the contents of said first digital counter describes a commanded position for said movable device in the reference frame and the contents of said second digit-al counter describes an instantaneous true position of said movable .device in the reference frame.

3. A comparator for comparing contents of a first (m-l-n)stage digital counter with that of a second (m-{-n)stage digital counter, comprising: a digital comparator section including means for comparing the contents of the m stages of the first and second digital counters and generating a first output signal of predetermined magnitude when the contents of the m stages of the first digital counter is greater than the contents of the m stages of the second digital counter, and generating a second `output signal of the same predetermined magnitude when the contents of the m stages of the second digital counter `is greater than the contents of the m stages of the first digital counter; an analogue comparator section including means for converti-ng the contents of the n stages of the first digital counter into a third output signal of magnitude proportional to the contents of the n stages thereof, and means for converting the contents of the n stages of the second digital counter into a fourth output signal of magnitude proportional to the contents 'of the n stages thereof, the third and fourth output signals having a predetermined magnitude smaller than the predetermined magnitude of the first and second output signals; means for combining the first and second output signals respectively with the third and fourth output signals; and means for comparing the magnitudes of the combined pairs of signals.

4. A comparator for comparing contents of a first (m-|-n)stage digital counter with that of a second (m}-n)stage digital counter, comprising: a digital comparator section including means for comparing the contents of the m stages of the first and second digital counters and generating a first output signal when the contents of the m stages of the first digital counter is greater than the contents of the m stages of the second digital counter, and generating a second output signal when the greater than the contents of the m stages of the first digital counter; an analogue comparator section including means for converting the contents of the n stagesof the first digital counter into a third output signal proportional to the contents of the n stages thereof, and means for converting the contents of the n stages of the second digital counter into a fourth output signal proportional to the contents of the n stages thereof; and means responsively energized in one mode of operation to the first and third output signals, and in another mode to the second and fourth output signals.

5. In a servo system, a first (m-l-n)stage digital counter; a second (rrz+n)-stage digital counter; a comparator having a digital section and an analogue section, the digital section including means for comparing the contents of the m stages of said first and second counters and generating a first output signal when the contents of the m stages of said first digital counter is greater than the contents of the m stages of said second digital counter, and generating a second output signal when the contents of the m stages of said second digital counter is greater than the contents of the m stages of said first digital counter, and the analogue comparator section including means for converting the contents of the n stages of said first digital counter into a third output signal proportional to the contents of the n stages thereof, means for converting the contents of the n stages of said second digital counter into a fourth output signal proportional to the contents of the n stages thereof, and means for combining the first, second, third and fourth output signals into two pairs of combined output signals; and an amplifier having the combined output signals applied thereto to provide an output signal of one polarity when the contents of said first digital counter is greater than that of said second ydigital counter and of reversed polarity when such condition is reversed.

6. The invention according to claim 5 wherein said digital comparator section includes, in addition, interlock means connected between the m comparator stages for preventing the generation of output signals from a next succeeding comparator stage until digit contents cornpared by an instant digital comparator stage are matched.

7. A comparator for comparing contents of a first (m-|-n)-stage digital counter with that `of a second (m-i-n)-stage digital counter, comprising: a digital comparator section including (m-l-n) comparator stages for respectively comparing individual stage contents of the (m-i-n) stages of the first and second digital counters, each said (m-l-n) comparator stages generating a first output signal when the contents of the respective stage of the first digital counter is greater than the contents of the corresponding stage of the second digital counter, and generating a second output signal when the contents of the respective stage of the second digital counter is greater than the contents of the corresponding stage of the first digital counter; analogue comparator section including n stages respectively receiving the first output signals 'of the n digital comparator stages and converting the same into 4a single third output signal proportional to the contents of the n stages of the first digital counter, and another n stages respectively receiving the second output signals of the n digital comparator stages and converting the same into a single fourth output signal proportional to the contents of the n stages thereof; means for combining the first, second, third and fourth output signals into two pairs of combined output signals; and amplifier means having the combined output signals applied thereto to provide an output signal therefrom of one polarity when the contents of said first digital counter is greater than that of said second digital counter, and of reversed polarity ywhen such condition is reversed.

8. The invention according to claim 7 wherein said digital comparator section includes, in addition, interlock means connected between iat least the m comparator stages for preventing the generation in such stages of output signals from a next succeeding digital comparator stage until digit contents compared by an instant digital comparator stage are matched.

9. In a servo system, a first (m-l-n)stage digital counter; a second (m-ln)stage digital counter; a comparator having a digital section and an analogue section, the digital section including (m4-11) comparator stages for respectively comparing the individual stage contents of the (m-l-n) stages of said first and second counters, each of said (m-l-n) comparator stages generating a first output signal when the contents of the respective stage of said first digital counter is greater than the contents of the corresponding stage of said second digital counter, and generating a second output signal when the contents of the respective stage of said second digital counter is greater than the contents of the corresponding stage of said first digital counter, and the analogue comparator section including n stages respectively receiving the first output signals of the n digital comparator stages and converting the saime into a single third output signal proportional to the contents of the n stages of said first digital counter, and another n stages respectively receiving the second output signals of Ithe n digital comparatorstages and converting the same into a single fourth output signal proportional to the contents of the n stages of said second digital counter; means for combining the first and second output signals of the mI digital comparator stages and the third and fourth output signals; and an operational amplifier having the combined output signals applied thereto to provide yan output signal therefrom of one polarity when the contents of said first digital counter is greater than that of said second digital counter, and of reversed polarity when such condition is reversed.

10. The invention according to claim 9 wherein said digital comparator section includes, in addition, interlock means connected between at least the m comparator stages for preventing the generation in such stages of output signals from a next succeeding digital comparator stage until digit contents compared by an instant digital comparator stage are matched.

11. The invention according to claim 9 including, in addition, a device movable within a reference frame, a servomotor adapted to drive and position said movable device in the reference frame, said servomotor being responsive in speed and direction respectively to the magnitude and polarity of the output signal of said operational amplifier, and wherein the contents of said first digital counter describes a commanded position for said movable device in the reference frame and the contents of said second digital counter describes an instantaneous true position of said movable device in the reference frame.

12. The invention according to claim 9 including, in addition, means responsive to the first and second output signals of the m digital comparator stages for generating a saturating output voltage in the output of said operational amplifier.

13. The invention according to claim 12 including, in addition, means for delaying generation of the saturating output voltage for a predetermined period of time.

i4. A comparator for comparing contents of a first nstage digital counter with that of a second n-stage digital counter and providing rst and second output signals for respectively indicating when the contents of the first digital counter is greater than that of the second digital counter and when such condition is reversed, comprising: n comparatorstages corresponding with the n stages of the first and second digital counters, each comparator stage including a first and second and circuit each having at least three inputs and an output, means for applying the output of a corresponding stage of the rst digital counter and the complement output thereof respectively to first inputs of said first and second and circuits, means for applying the output of a corresponding stage of the second digital counter and the complement output thereof respectively to second inputs of said first and said second and circuits, first output 4means of the instant comparator stage connected to the output of said rst and circuit, econd output means of the instant comparator stage connected to the output of said second and circuit, and interlock means responsive to the outputs of said first and second and circuits and having an output connected to third inputs of said first and second and circuits of a next succeeding comparator stage for controlling output from the first and second output means of the next succeeding comparator stage, an output being obtainable from the next succeeding comparator stage when the outputs respectively from corresponding stages of the first and second digital counters are matched, said interlock means comprising an or circuit having first, second and third inputs and an output, said or circuit providing a high output voltage for high input voltages to any of the three inputs, the first and second inputs of said or circuit 4being connected respectively to the outputs of said first and second and circuits, means connecting a high input voltage to the third inputs of the rst and second and circuits of the next succeeding comparator stage, means connecting a low clamping voltage to the third input of the or circuit of the next succeeding comparator stage, switching means for converting the high input voltage to a low clamping voltage to the third inputs of the first and second and circuits of the next succeeding comparator stage and for converting the low clamping voltage to a high input voltage to the third input of the or circuit of the next succeeding comparator stage, said switching means being connected to the output of said or circuit and operably responsive to a high output voltage therefrom, whereby the low clamping voltage to the third inputs of the first and second and circuits of the next succeeding comparator stage is applied to clamp the outputs thereof to zero output and the high input voltage to the third input of the or circuit of the next succeeding comparator stage produces a high output voltage therefrom to operate switching means of the next succeeding comparator stage, when said switching means of the instant comparator stage is operated.

15. A comparator for comparing contents of a first (m-l-n)stage digital counter with that of a second (ml-n)-stage digital counter, comprising: a digital comparator section including means for comparing the contents of the m stages of the first and second digital counters and generating a first output signal when the contents of the m stages of the first digital counter is greater than the contents of the m stages of the second digital counter, and generating a second output signal when the contents of the m stages of the second digital counter is greater than the contents of the m stages of the first digital counter, and interlock means connected between the m comparator stages for preventing generation of output signals from .a next succeeding comparator stage until digit contents compared by an instant digital comparator stage are matched; an analogue comparator section including means for converting the contents of the n stages of the first digital counter into a third output signal proportional to the contents of the n stages thereof, and means for converting the contents of the n stages of the second digital counter into a fourth output signal proportional t0 the contents of the n stages thereof; 'and means responsively energized in one mode of operation to the first and third output signals, and in another mode to the second and fourth output signals..

References Cited in the file of this patent UNITED STATES PATENTS 2,844,309 Ayres July 22, 1958r 2,885,659 Spielberg May 5, 1959 2,907,003 Hobbs Sept. 29, 1959 2,927,258 Lippel Mar. 1, 1960 2,953,773 Di Nicolantonio Sept. 20, 196() 

1. IN A SERVO SYSTEM, A FIRST (M+N)-STAGE DIGITAL COUNTER; A SECOND (M+N)-STAGE DIGITAL COUNTER; A COMPARATOR HAVING A DIGITAL SECTION AND AN ANALOGUE SECTION, THE DIGITAL SECTION INCLUDING MEANS FOR COMPARING THE CONTENTS OF THE M STAGES OF SAID FIRST AND SECOND COUNTERS AND GENERATING A FIRST OUTPUT SIGNAL OF PREDETERMINED MAGNITUDE WHEN THE CONTENTS OF THE M STAGES OF SAID FIRST DIGITAL COUNTER IS GREATER THAN THE CONTENTS OF THE M STAGES OF SAID SECOND DIGITAL COUNTER, AND GENERATING A SECOND OUTPUT SIGNAL OF THE SAME PREDETERMINED MAGNITUDE WHEN THE CONTENTS OF THE M STAGES OF SAID SECOND DIGITAL COUNTER IS GREATER THAN THE CONTENTS OF THE M STAGES OF SAID FIRST DIGITAL COUNTER, AND THE ANALOGUE COMPARATOR SECTION INCLUDING MEANS FOR CONVERTING THE CONTENTS OF THE STAGES SAID FIRST DIGITAL COUNTER INTO A THIRD OUTPUT SIGNAL OF MAGNITUDE PROPORTIONAL TO THE CONTENTS OF THE THE N STAGES THEREOF, MEANS FOR CONVERTING THE CONTENTS OF THE N STAGES OF SAID SECOND DIGITAL COUNTER INTO A FOURTH OUTPUT SIGNAL OF MAGNITUDE PROPORTIONAL TO THE CONTENTS OF THE N STAGES THREROF, THE THIRD AND FOURTH OUTPUT SIGNALS HAVING A PREDETERMINED MAXIMUM MAGNITUDE SMALLER THAN THE PREDETERMINED MAGNITUDES OF THE FIRST AND SECOND OUTPUT SIGNALS, AND MEANS FOR COMBINING THE FIRST AND SECOND OUTPUT SIGNALS RESPECTIVELY WITH THE THIRD AND FOURTH OUTPUT SIGNALS; AND A DIFFERENTIAL OPERATIONAL AMPLIFIER HAVING THE COMBINED OUTPUT SIGNALS APPLIED THERETO A PROVIDE AN OUTPUT SIGNAL OF ONE POLARITY WHEN THE CONTENTS OF SAID FIRST DIGITAL COUNTER IS GREATER THAN THAT OF SAID SECOND DIGITAL COUNTER AND OF REVERSED POLARITY WHEN SUCH CONDITION IS REVERSED, THE OUTPUT SIGNAL OF SAID DIFFERNTIAL OPERATIONAL AMPLIFIER BEING PROPORTIONAL TO THE DIFFERENCE IN MAGNITUDE OF THE COMBINED SIGNAL PAIRS. 